FPGA design flow becomes more and more a software based designflow. Till recently FPGA designers used VHDL/Verilog as a design entry language, while now languages as C/
C++, OpenCL or SystemC are more common. The latest generation Xilinx MPSoC FPGAs has integrated ARMand GPU cores as well as a variety of IP blocks that needs to be software
controlled. The Xilinx SDSoC tool helps the FPGA designer to accelerate hissoftware design by moving selected software functions to FPGA hardware resources. This presentation gives you
a quick overview how this is done.
Frank de Bont, Core|vision